Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding

Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed. A methodology to measure die shift was developed and applied to create maps of die shift on an 8 inch wafer. A total of 256 dies were embedded in an 8 inch mold compound wafer using compression molding. Thermal and cure shrinkages of mold compound are determined to be the primary reasons for die shift in wafer molding. Die shift value increases as the distance from the center of the wafer increases. Pre-compensation of die shift during pick and place is demonstrated as an effective method to control die shift. Applying pre-compensation method 99% of dies can be achieved to have die shift values of less than 40 μm. Usage of carrier wafer during wafer molding reduces the maximum die shift in a wafer from 633 μm to 79 μm. Die area/package area ratio has a strong influence on the die shift values. Die area/package area ratios of 0.81, 0.49, and 0.25 lead to maximum die shift values of 26, 76, and 97 μ.m, respectively. Wafer molding using low coefficient of thermal expansion (7 × 10-6/°C) and low cure shrinkage (0.094%) mold compounds is demonstrated to yield maximum die shift value of 28 μm over the whole 8 inch wafer area.

[1]  B. Keser,et al.  Advanced Packaging: The Redistributed Chip Package , 2007, IEEE Transactions on Advanced Packaging.

[2]  V. Kripesh,et al.  150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects , 2008, IEEE Transactions on Advanced Packaging.

[4]  Xiaowu Zhang,et al.  Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP) , 2008, Microelectron. Reliab..

[5]  M. Brunnbauer,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

[6]  V. N. Sekhar,et al.  Wafer level embedding technology for 3D wafer level embedded package , 2009, 2009 59th Electronic Components and Technology Conference.

[7]  H. Hedler,et al.  An embedded device technology based on a molded reconfigured wafer , 2006, 56th Electronic Components and Technology Conference 2006.

[8]  A. Kumar,et al.  Design and development of a multi-die embedded micro wafer level package , 2008, 2008 58th Electronic Components and Technology Conference.