Efficient RNS to binary conversion using high-radix SRT division
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This paper proposes a new CRT-based technique for the conversion of residue numbers to binary representation that employs a high-radix radix r SRT division-like architecture. The major benefit of the new technique is that it permits the efficient, low-latency conversion of residue numbers with many moduli. A k-modulus RNS converter returning a w-bit result employs k+1 ROM's with restricted address space, a k-input carry-save addition tree, a (2 log/sub 2/r)-bit carry-propagate adder, and one (w+log/sub 2/k)-bit carry-propagate subtractor. This comprises, to our knowledge, less hardware than any other reported general modulus CRT-based converter.
[1] K. Elleithy,et al. Fast and flexible architectures for RNS arithmetic decoding , 1992 .
[2] Graham A. Jullien,et al. A fast VLSI systolic array for large modulus residue addition , 1994, J. VLSI Signal Process..
[3] Neil Burgess,et al. Choices of Operand Truncation in the SRT Division Algorithm , 1995, IEEE Trans. Computers.
[4] I. Koren. Computer arithmetic algorithms , 2018 .
[5] Bruce E. Litow,et al. Fast Parallel Arithmetic via Modular Representation , 1991, SIAM J. Comput..