Parameter optimization of an on-chip voltage reference circuit using evolutionary programming

This paper presents an application of evolutionary programming to parameter optimization in the design of a voltage reference circuit. Designing circuits consists of two steps: topological design and parameter determination. After designing a topology suitable for the circuit, the designer selects an appropriate value for each circuit element from a circuit analysis and his experience. This step is difficult and time consuming because the designer must consider many factors simultaneously. As more precise circuits are required, parameter optimization becomes more complex. The voltage reference circuit, which requires a precise reference voltage independent of power fluctuation and temperature change, is such an example. In this paper, evolutionary programming is used as an effective method of finding good parameter values for the elements of the voltage reference circuit. Simulation results show that this method provides good performance and can be used as an effective method for circuit design.

[1]  Masashi Horiguchi,et al.  Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test , 1991 .

[2]  L. C. Stayton,et al.  On the effectiveness of crossover in simulated evolutionary optimization. , 1994, Bio Systems.

[3]  Zbigniew Michalewicz,et al.  Genetic algorithms + data structures = evolution programs (3rd ed.) , 1996 .

[4]  Peter J. Fleming,et al.  An Overview of Evolutionary Algorithms in Multiobjective Optimization , 1995, Evolutionary Computation.

[5]  Katsuro Sasaki,et al.  A voltage down converter with submicroampere standby current for low-power static RAMs , 1992 .

[6]  Beomsup Kim,et al.  Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach , 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

[7]  Dongkyung Nam,et al.  Parameter optimization of a voltage reference circuit using EP , 1998, 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360).

[8]  Tanaka Haruhiko,et al.  Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMs , 1994 .

[9]  David B. Fogel,et al.  Tuning Evolutionary Programming for Conformationally Flexible Molecular Docking , 1996, Evolutionary Programming.

[10]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[11]  Emile H. L. Aarts,et al.  Simulated Annealing: Theory and Applications , 1987, Mathematics and Its Applications.

[12]  O. Nelles,et al.  An Introduction to Optimization , 1996, IEEE Antennas and Propagation Magazine.

[13]  K. Kajigaya,et al.  A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[14]  E. Chong,et al.  Introduction to optimization , 1987 .