The Integration of SystemC and Hardware-Assisted Verification

In this research a refined interface between high-level design languages and hardware verification platforms is developed. Our interface methodology is demonstrated through the integration of a communication system design, written in C and SystemC, with a multi-FPGA logic emulator from Ikos Systems. We show that as designs are refined from a high-level to a gate-level representation, our methodology improves verification performance while maintaining verification fidelity across a range of abstraction levels.

[1]  S. Wicker.  Error Control Systems for Digital Communication and Storage , 1994 .

[2]  Soha Hassoun,et al.  A transaction-based unified simulation/emulation architecture for functional verification , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[3]  Abhijit Ghosh,et al.  Methodology for hardware/software co-verification in C/C++ (short paper) , 2000, ASP-DAC '00.

[4]  Abhijit Ghosh,et al.  Methodology for hardware/software co-verification in C/C++ , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).