A 2.5-V 16-Mb DRAM in 0.5-/spl mu/m CMOS technology

Low-voltage circuit techniques for high-density DRAMs, and the utilization of these techniques on a 16-Mb DRAM operating over the 2.5-V specification range, are presented. The P-type array is designed using full-V/sub cc/ bit line precharge for fast signal development and optimal sense latch sensitivity. Performance and power are further enhanced by using a digital secondary sense amplifier (DSSA). A worst-case module access of 55 ns is obtained from chips fabricated in 0.5-/spl mu/m CMOS technology.

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