Efficiently High Speed Implementation of AES Algorithm on FPGA

With the increasing number of internet and wireless communication users in any organisation, data security has become a major problem for the valuable information that needs to be protected. So to protect the user data that is being transmitted over open channels some means of resilient data protection is needed. So AES can be considered as the most widely used modern symmetric key encryption standard for such sensitive data that needs to be kept secured. This paper propounds high speed implementation of AES algorithm while maintain with the minimum amount of hardware resources. The proposed AES algorithm supports 128 bit key length. In order to achieve high speed pipelined architecture is used. The AES-128 design is implemented on FPGA with XC6SLX16-3CSG324 package using Verilog language with the help of Xilinx ISE tool.

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