FPGA based sliding window architecture for RC5 encryption

In the current scenario, security for the data has more of its concern. Many encryption algorithms have been proposed to satisfy certain levels of security issues and known for their cryptographic strengths. The extensive use of reconfigurable processors like FPGA for cryptographic applications has made the design and testing of hardware logic simple. This paper introduces, a new sliding window based hardware architecture in Xilinx FPGA for RC5 cryptographic algorithm modeled to satisfy the response and waiting time. This is done to provide faster encryption thereby reducing the risk of deadline miss. The performance comparison between implementation of various RC5 architectures based on area and delay are graphed.

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