Virtual flash chips: Rethinking the layer design of flash devices to improve data recoverability

The market trend of flash memory chips has been going for high density but low reliability. The rapidly increasing bit error rates and emerging reliability issues of the coming triple-level cell (TLC) and even three-dimensional (3D) flash chips would let users take an extremely high risk to store data in such low reliability storage media. With the observations in mind, this paper rethinks the layer design of flash devices and propose a complete paradigm shift to re-configure physical flash chips of potentially massive parallelism into better “virtual chips”, in order to improve the data recoverability in a modular and low-cost way. The concept of virtual chips is realized at hardware abstraction layer (HAL) without continually complicating the conventional flash management software (i.e., flash translation layer (FTL)). The capability and compatibility of the proposed design are then verified by a series of experiments with encouraging results.

[1]  Nikolai Joukov,et al.  A nine year study of file system and storage benchmarking , 2008, TOS.

[2]  Zili Shao,et al.  An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems , 2011, 2011 Design, Automation & Test in Europe.

[3]  Tei-Wei Kuo,et al.  A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[4]  Yi Qin,et al.  A Parity Scheme to Enhance Reliability for SSDs , 2012, 2012 IEEE Seventh International Conference on Networking, Architecture, and Storage.

[5]  Tei-Wei Kuo,et al.  Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  Hong Jiang,et al.  Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance , 2013, IEEE Transactions on Computers.

[7]  Dongkun Shin,et al.  Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD , 2011, IEEE Transactions on Computers.

[8]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[9]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..

[10]  Zili Shao,et al.  MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[12]  Paul H. Siegel,et al.  Characterizing flash memory: Anomalies, observations, and applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[13]  David Hung-Chang Du,et al.  Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead , 2011, 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST).

[14]  Nikil D. Dutt,et al.  A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.