This paper describes several enhancements and various applications of a versatile and extensible software tool called QUI2VER to support integration of custom components for research prototyping in programmable logic. From higher-level specifications of components and interconnections in an input file, QUI2VER generates an output VHDL file with a desired system configuration. The value of QUI 2VER stems from how abstract interfaces can be specified in support of component interconnection for system-level configuration. We have enhanced QUI2VER with multidimensional array-based and loop-based system specification capabilities. We have included enhanced support for symbolic constants, generic parameters, and arbitrary arithmetic expressions. We have also created a graphical tool to visualize component interface definitions and to support graphical system specification based on such interfaces. We demonstrate our enhancements by using QUI2VER to generate systems for single-chip implementation in programmable logic using our own intellectual property, including multidimensional interconnection networks, an extensible embedded processors and a sophisticated cache-coherent multiprocessor based on our own custom pipelined 32-bit processors, split-transaction bus components, and memory components
[1]
M. Sinnathamby,et al.
A versatile component integration tool for rapid prototyping in programmable logic
,
2005,
Canadian Conference on Electrical and Computer Engineering, 2005..
[2]
Huang Jin,et al.
Architecture and implementation of chip multiprocessors: custom logic components and software for rapid prototyping
,
2004,
International Conference on Parallel Processing, 2004. ICPP 2004..
[3]
N. Manjikian,et al.
A versatile memory-interface architecture for enhancing performance of video applications
,
2005,
The 3rd International IEEE-NEWCAS Conference, 2005..
[4]
Stuart Sutherland,et al.
Systemverilog For Design
,
2003
.
[5]
N. Manjikian,et al.
Prototype hardware implementation of a single-chip multiprocessor with a split-transaction bus
,
2005,
PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005..