Direct digital frequency synthesis with dual-slope approach

A new technique for phase to sine mapping in direct digital frequency synthesizers (DDFSs) is presented. With respect to previously proposed piecewise linear Taylor and Chebyshev approaches, novel technique reduces either ROM size or arithmetic hardware complexity, without decreasing accuracy. Simulation results for a 0.35/spl mu/m technology show a substantial increase in performances with respect to Taylor and Chebyshev DDFSs.

[1]  H. Samueli,et al.  A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .

[2]  M. Waltari,et al.  A direct digital synthesizer with an on-chip D/A-converter , 1998, Proceedings of the 23rd European Solid-State Circuits Conference.

[3]  Mostafa M. El Said,et al.  An improved ROM compression technique for direct digital frequency synthesizers , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  A.G.M. Strollo,et al.  Direct digital frequency synthesizers using first–order polynomial Chebyshev approximation , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[5]  J. Niittylahti,et al.  Low-power direct digital frequency synthesizer , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[6]  H. Samueli,et al.  An 800 MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 /spl mu/m CMOS , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[7]  D. De Caro,et al.  Direct digital frequency synthesizers using high-order polynomial approximation , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  A. Y. Kwentus,et al.  A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range , 1999, IEEE J. Solid State Circuits.

[9]  Jouko Vankka.  1996 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM METHODS OF MAPPING FROM PHASE TO SINE AMPLITUDE IN DIRECT DIGITAL SYNTHESIS , 1996 .

[10]  Davide De Caro,et al.  ROM-less direct digital frequency synthesizers exploiting polynomial approximation , 2002, 9th International Conference on Electronics, Circuits and Systems.

[11]  Jalil Fadavi-Ardekani.  M×N Booth encoded multiplier generator using optimized Wallace trees , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Bar-Giora Goldberg.  Digital Frequency Synthesis Demystified: DDS and Fractional-n Plls , 1999 .