Design rules for implementing CORDIC on FPGAs

The CORDIC algorithm performs vector rotations in a number of coordinates systems, providing cost-effective solutions for many application domains today including intelligent guidance systems, wireless communications, and digital signal processing. CORDIC is sequential; thus hardware solutions are needed to improve the computation speed. We analyze three implementation schemes for CORDIC on FPGAs in terms of area, delay, and scalability. Extensive simulations have been carried out and a complete set of numerical figures are provided. We conclude the paper by proposing a number of design rules for implementing CORDIC on commercial reconfigurable devices based on use-case and speed and/or area requirements.

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