Fast mixed-mode simulation for accurate MOS bridging fault detection

A dynamic mixed-mode approach for the simulation of physical faults in MOS VLSI circuits is described, with emphasis on bridging faults. Bridging faults in digital circuits could cause the affected gates or subcircuits, and possibly their immediate fanouts, to behave as analog subcircuits in a localized region within a design. Mixed digital gate-level and switch-level simulation with dynamic localized analog simulation, depending on the location of a fault, provides a robust and fast way to perform digital fault simulation accurately and fast enough for practical fault simulation.<<ETX>>

[1]  Prathima Agrawal,et al.  Automatic modeling of switch-level networks using partial orders , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[2]  Resve A. Saleh,et al.  Mixed-mode incremental simulation and concurrent fault simulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  Tracy Larrabee,et al.  Testing for parametric faults in static CMOS circuits , 1990, Proceedings. International Test Conference 1990.

[4]  Prathima Agrawal,et al.  Automatic modeling of switch-level networks using partial orders [MOS circuits] , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Resve Saleh,et al.  Simulation and analysis of transient faults in digital circuits , 1992 .

[6]  Ibrahim N. Hajj,et al.  A switch-level matrix approach to transistor-level fault simulation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[7]  Ibrahim N. Hajj An algebra for switch-level simulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Gerald E. Sobelman,et al.  Fast switch-level fault simulation using functional fault modeling , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.