Time redundancy based soft-error tolerance to rescue nanometer technologies

The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the reliable operation of very deep submicron ICs. The effects of various noise sources are becoming of great concern. In particularly, it is predicted that single event upsets induced by alpha particles and cosmic radiation will become a cause of unacceptable error rates in future very deep submicron and nanometer technologies. This problem, concerning in the past more often parts used in space, will affect future ICs at sea level. This challenging problem has to be solved otherwise technological progress will be blocked soon. Thus, fault tolerant design is becoming necessary, even for commodity applications. But economic constraints of commodity applications exclude the use of traditional, high-cost fault tolerant techniques. This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks.

[1]  Michael Nicolaidis,et al.  A theory of perturbation tolerant asynchronous FSMs and its application on the design of perturbation tolerant memories , 1997 .

[2]  M. Baze,et al.  Comparison of error rates in combinational and sequential logic , 1997 .

[3]  M. Baze,et al.  Attenuation of single event induced pulses in CMOS combinational logic , 1997 .

[4]  Michael Nicolaidis.  Scaling deeper to submicron: on-line testing to the rescue , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[5]  Michael Nicolaidis,et al.  On-line testing for VLSI: state of the art and trends , 1998, Integr..

[6]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[7]  R. Velazco,et al.  Design of SEU-hardened CMOS memory cells: the HIT cell , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[8]  Michael Nicolaidis.  Design for soft-error robustness to rescue deep submicron scaling , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Prithviraj Banerjee,et al.  RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[10]  W. W. Peterson.  On Checking an Adder , 1958, IBM J. Res. Dev..

[11]  Thammavarapu R. N. Rao,et al.  Error coding for arithmetic processors , 1974 .

[12]  Algirdas Avizienis,et al.  Arithmetic Algorithms for Error-Coded Operands , 1973, IEEE Transactions on Computers.

[13]  Nur A. Touba,et al.  Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[14]  Michael Nicolaidis,et al.  A CAD framework for generating self-checking multipliers based on residue codes , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[15]  Jr. Leonard R. Rockett.  An SEU-hardened CMOS data latch design , 1988 .

[16]  J. Canaris,et al.  SEU hardened memory cells for a CCSDS Reed-Solomon encoder , 1991 .