Event recognition hardware based on neuron MOS soft-computing circuits

Abstract Neuron MOS transistor (neuMOS or νMOS) mimicking the fundamental behavior of neurons at a primitive device level allows the implementation of intelligent functions directly on the integrated circuit hardware. Based on the νMOS technology a real-time event recognition system has been developed. A neuron MOS association processor searches for the event in the past memory having the maximum similarity to the current event presented to the system. This is based on Manhattan-distance calculation and the minimum distance search by a winner-take-all (WTA) circuitry. The computation is carried out directly on the hardware in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing past events in multi-valued vectors. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. The νMOS circuit operation is characterized by analog computation directly conducted on an electrically floating node which is immediately followed by the thresholding action of a transistor to yield a binary decision. νMOS circuits would provide an opportunity for a very flexible soft computing scheme, while preserving the rigorous nature of digital processing.

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