Data compression with restricted parsings

We consider a class of algorithms related to Lempel-Ziv that incorporate restrictions on the manner in which the data can be parsed with the goal of introducing new tradeoffs between implementation complexity and data compression ratios. Our main motivation lies within the field of compressed memory computer systems. Here requirements include extremely fast decompression and compression speeds, adequate compression performance on small data block lengths, and minimal hardware area and energy requirements. We describe the approach and provide experimental data concerning its compression performance with respect to known alternatives. We show that for a variety of data sets stored in a typical main memory, this direction yields results close to those of earlier techniques, but with significantly lower energy consumption at comparable or better area requirements. The technique thus may be of eventual interest for a number of applications requiring high compression bandwidths and efficient hardware implementation

[1]  T. Iwasaki,et al.  A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  James A. Storer,et al.  Parallel algorithms for data compression , 1985, JACM.

[3]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[4]  Michael E. Wazlowski,et al.  IBM Memory Expansion Technology (MXT) , 2001, IBM J. Res. Dev..

[5]  Glen G. Langdon,et al.  An Introduction to Arithmetic Coding , 1984, IBM J. Res. Dev..

[6]  James A. Storer,et al.  Data compression via textual substitution , 1982, JACM.

[7]  James A. Storer,et al.  A Parallel Architecture for High-Speed Data Compression , 1991, J. Parallel Distributed Comput..

[8]  En-Hui Yang,et al.  Grammar-based codes: A new class of universal lossless source codes , 2000, IEEE Trans. Inf. Theory.

[9]  John T. Robinson,et al.  Parallel compression with cooperative dictionary construction , 1996, Proceedings of Data Compression Conference - DCC '96.

[10]  Nagarajan Ranganathan,et al.  High-speed VLSI designs for Lempel-Ziv-based data compression , 1993 .

[11]  Krste Asanovic,et al.  Banked multiported register files for high-frequency superscalar microprocessors , 2003, ISCA '03.

[12]  Philip Heidelberger,et al.  Algorithms and data structures for compressed-memory machines , 2001, IBM J. Res. Dev..

[13]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[14]  D. J. Wheeler,et al.  A Block-sorting Lossless Data Compression Algorithm , 1994 .