Bringing Automated Model Checking to PLC Program Development - a CERN Case Study

Abstract Verification of critical software is a high priority but a challenging task for industrial control systems. Model checking appears to be an appropriate approach for this purpose. However, this technique is not widely used in industry yet, due to some obstacles. The main obstacles encountered when trying to apply formal verification techniques at industrial installations are the difficulty of creating models out of PLC programs and defining formally the specification requirements. In addition, models produced out of real-life programs have a huge state space, thus preventing the verification due to performance issues. Our work at CERN (European Organization for Nuclear Research) focuses on developing efficient automatic verification methods for industrial critical installations based on PLC (Programmable Logic Controller) control systems. In this paper, we present a tool generating automatically formal models out of PLC code. The tool implements a general methodology which can support several input languages, like the PLC programming languages defined in the IEC 61131 standard, as well as the model formalisms of different model checker tools. The tool supports the three main stages of model checking: system modelization, requirement formalization and counterexample analysis. In addition, a verification case study of a PLC program, written in Structured Text (ST) language implemented at CERN is described. The paper shows that the verification process is automatized and supported by the proposed tool, thus its difficulty is completely hidden for the control engineer.

[1]  Joseph Sifakis,et al.  Rigorous Component-Based System Design Using the BIP Framework , 2011, IEEE Software.

[2]  Lothar Litz,et al.  Formal methods in PLC programming , 2000, Smc 2000 conference proceedings. 2000 ieee international conference on systems, man and cybernetics. 'cybernetics evolving to systems, humans, organizations, and their complex interactions' (cat. no.0.

[3]  Víctor M. González Suárez,et al.  Formal Verification of Complex Properties on PLC Programs , 2014, FORTE.

[4]  Thomas Noll,et al.  Speeding Up the Safety Verification of Programmable Logic Controller Code , 2013, Haifa Verification Conference.

[5]  Junbeom Yoo,et al.  A Verification Framework for FBD Based Software in Nuclear Power Plants , 2008, 2008 15th Asia-Pacific Software Engineering Conference.

[6]  José Machado,et al.  Property Patterns for the Formal Verification of Automated Production Systemsstar , 2008 .

[7]  Heiko Behrens,et al.  Xtext: implement your language faster than the quick and dirty way , 2010, SPLASH/OOPSLA Companion.

[8]  Jan Sadolewski Conversion of ST Control Programs to ANSI C for Verification Purposes , 2011, e Informatica Softw. Eng. J..

[9]  Dániel Darvas,et al.  Transforming PLC Programs into Formal Models for Verification Purposes , 2013 .

[10]  Rolf Drechsler,et al.  VERIFICATION OF PLC PROGRAMS USING FORMAL PROOF TECHNIQUES , 2008 .

[11]  Benjamin Bradu,et al.  UNICOS EVOLUTION: CPC VERSION 6 , 2011 .

[12]  Jan Sadolewski Automated conversion of ST control programs to why for verification purposes , 2011, 2011 Federated Conference on Computer Science and Information Systems (FedCSIS).

[13]  Stephan Merz,et al.  Model Checking , 2000 .

[14]  Hans-Dieter Ehrich,et al.  Model Checking PLC Software Written in Function Block Diagram , 2010, 2010 Third International Conference on Software Testing, Verification and Validation.

[15]  Philippe Schnoebelen,et al.  Towards the automatic verification of PLC programs written in Instruction List , 2000, Smc 2000 conference proceedings. 2000 ieee international conference on systems, man and cybernetics. 'cybernetics evolving to systems, humans, organizations, and their complex interactions' (cat. no.0.

[16]  V. Gourcuff,et al.  Improving large-sized PLC programs verification using abstractions , 2008 .

[17]  Olaf Stursberg,et al.  Verification of PLC Programs Given as Sequential Function Charts , 2004, SoftSpez Final Report.

[18]  J.-M. Faure,et al.  Efficient representation for formal verification of PLC programs , 2006, 2006 8th International Workshop on Discrete Event Systems.

[19]  Marco Pistore,et al.  NuSMV 2: An OpenSource Tool for Symbolic Model Checking , 2002, CAV.

[20]  Frank Budinsky,et al.  EMF: Eclipse Modeling Framework 2.0 , 2009 .

[21]  Stefan Kowalewski,et al.  Counterexample-Guided Abstraction Refinement for PLCs , 2010, SSV.

[22]  Wang Yi,et al.  UPPAAL - Now, Next, and Future , 2000, MOVEP.

[23]  Joseph Sifakis,et al.  Rigorous Component-Based System Design - (Invited Paper) , 2012, WRLA.