Evaluation of Digital LLRF Control System Performance at STF in KEK

The Superconducting RF Test Facility (STF) at the High Energy Accelerator Research Organization (KEK) was built for research and development of the International Linear Collider (ILC). Several digital low-level radio frequency (LLRF) control systems were developed at the STF. The purposes of these developments are to construct a minimal configuration of the ILC LLRF system and achieve the amplitude and phase stability of the accelerating field in the superconducting accelerator. Evaluations of digital LLRF control systems were conducted during the conditioning of eight superconducting cavities performed between October and November 2016. The digital LLRF control system configured for ILC was demonstrated and the performance fulfilled the required stability criteria of the accelerating field in the ILC. These evaluations are reported in this paper. INTRODUCTION A field programmable gate array (FPGA)-based digital low-level radio frequency (LLRF) control system will be employed in the International Linear Collider (ILC) to achieve the radio frequency (RF) stability requirements. The amplitude and phase stabilities of 0.07%(RMS) and 0.35 °(RMS), respectively, are required for ILC [1]. For the acceleration, the ILC utilizes 1.3GHz superconducting RF cavities, operating at an average gradient of 31.5MV/m. The RF system will be organized in approximately 400 RF stations. Each RF station is composed of one 10MW multi-beam klystron driving 39 superconducting cavities. The feedback control is implemented to compensate the non-repetitive disturbance and measurement noise. As only a single klystron is used to drive 39 cavities, the digital LLRF control system has to control the vector sum of the accelerating field of those cavities. The vector sum is the sum of the complex vectors representing the accelerating fields of all cavities. The size of one RF station in the ILC is approximately 60m in length, which may add a delay to the signal transmission from cavity to digital LLRF control system. One possible solution to reduce this problem is to distribute the LLRF control system into several sub-systems, in a master–slave configuration. The slave LLRF control systems calculate partial vector sums from the corresponding cavities and are placed near the cavities to shorten the signal transmission lines. The partial vector sums from all slave LLRF control systems are sent to the master LLRF control system via an ∗ sigitbw@post.kek.jp Figure 1: STF layout consists of normal conducting photocathode RF gun, two superconducting 9-cell cavities in the capture cryomodule driven by 800 kW klystron, eight superconducting 9-cell cavities (cavity number 1 ∼ 8) in the CM-1 cryomodule, four superconducting 9-cell cavities in the CM2a cryomodules (cavity number 9 ∼ 12). Both CM-1 and CM-2a cryomodules are driven by one 10MW multi-beam klystron. optical communication link. One issue in this connection is the additional delay to the control loop caused by optical communication link, which may lead to system instability. This paper presents an evaluation of the digital LLRF control system with a master–slave configuration and an investigation to confirm the effect of the optical communication link delay on the RF stabilities. The demonstration of the minimum setup of digital LLRF control system with the master–slave configuration for the ILC was conducted at Superconducting RF Test Facility (STF)-High Energy Accelerator Research Organization (KEK) during the cavity conditioning in the autumn of 2016. The layout of the STF is illustrated in Figure 1. A total of twelve cavities in two cryomodules, CM-1 and CM-2a, were installed as the STF-2 project [2]. DIGITAL LLRF CONTROL SYSTEM WITH MASTER–SLAVE The LLRF control systemwith master–slave configuration will be adopted in ILC. Figure 2 shows the proposed system for one RF station. As a slave, the LLRF front-end controller calculates a partial vector sum from the corresponding cavities and the result is sent to the central LLRF controller as a master, where the total vector sums are calculated and the klystron output are controlled. In order to accommodate large data transfer from the front-end to the central system, an optical communication link is used. The minimum setup of the digital LLRF control system with master–slave configuration for ILC was built at STFTHPAB116 Proceedings of IPAC2017, Copenhagen, Denmark ISBN 978-3-95450-182-3 3992 Co py rig ht © 20 17 CC -B Y3. 0 an d by th er es pe ct iv ea ut ho rs 06 Beam Instrumentation, Controls, Feedback and Operational Aspects T27 Low Level RF Figure 2: Digital LLRF control system with master–salve configuration for the ILC. As a slave, the LLRF front-end controllers directly measure the signals from corresponding cavities and send the result to central LLRF controller as a master [1]. KEK, which is illustrated in Figure 3. The 1300MHz signals from the cavities are down-converted by mixing with 1310MHz local oscillator (LO) to get a 10MHz intermediate frequency (IF). After being digitized by the analog-todigital converter (ADC), the IF signal is converted into an in-phase component (I) and quadrature-phase component (Q) [3]. In the slave digital LLRF board, the partial vector sum of VS2 from corresponding cavities are calculated and sent to the master digital LLRF board through an optical communication link with an approximate length of 20m. In the master digital LLRF board, the total vector sum from partial vector sum of VS1 and VS2 is calculated. The delay introduced by the optical communication link can be compensated by introducing an additional delay in the partial vector sum of VS1 through the DLY module. To suppress the parasitic modes in the multi-cell cavities, a fourth-order conjugate poles digital infinite impulse response (IIR) filter [4] with a bandwidth of 250 kHz was implemented after the total vector sum calculation. The feedback and feedforward control algorithms are also performed in the master LLRF board. The digital signal is then converted into analog by a digital-to-analog converter (DAC) and is fed to the I/Q modulator to modulate the 1.3GHz RF signal from the master oscillator (MO). This signal is then used to drive the klystron, which drives the cavities. Both master and slave board are MTCA.4 standard hardware with 14-ch 16-bit AD9650 ADC (Analog Device, Inc.), 2-ch 16-bit AD9783 DAC (Analog Device, Inc.), and two FPGAs, Zynq-7000 and Spartan 6 (Xilinx Inc.). These boards employ 162.5MHz for FPGA clock and 81.25MHz for ADC/DAC clock.