Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Coarse-grained reconfigurable architectures deliver high performance and energy efficiency for computationally intensive applications like mobile multimedia and wireless communication. This work deals with the aspect of power-efficient dynamic reconfiguration control techniques in such architectures. Proper clock domain partitioning with custom clock gating combined with automatic clock gating resulted in a 38% total power reduction. This is more than a threefold as compared to the single clock gating techniques applied separately. One of the corresponding case study applications with 0.064 milliwatts per megahertz and 124 million operations per second per milliwatt power efficiency outperforms the major coarse-grained and general purpose embedded processor architectures by a factor of 1.7 to 28.