A method for error detection in the cryptographic transforming binary data and circuitry

The invention relates to a method for error detection in the cryptographic transforming input binary data into binary output data using a cryptographic circuit comprising n binary inputs for receiving the binary input data and m binary outputs for outputting the binary output data, and a circuit arrangement for carrying out the process. Within the framework of the cryptographic transforming the input binary data into the binary output data is a binary data transformation is performed by means of a encompassed by the cryptographic circuit subcircuit. Based on the binary input data to at least a portion of the n binary inputs of the cryptographic circuit is an input parity P is formed. An output parity PA on the basis of the binary output data to at least one part of the m binary outputs is also determined. The input parity P is then converted into a function of the running in the sub-circuit, binary data transformation using a parity conversion into a modified parity MP. For fault detection, the output parity PA and the modified parity MP are compared, wherein a fault is detected when it is determined that the output parity PA is different from the modified parity MP.