Low power 8T SRAM using 32nm independent gate FinFET technology

In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be biased differently to control the current and the device threshold voltage. By controlling the back gate of FinFET, SRAM cell can be designed for minimum power consumption. This paper proposes a new 8T (8 transistors) SRAM structure that reduces dynamic power in writing operation and provides wider SNM (static noise margin). Using the new FinFET based 8T SRAM cell, dynamic power consumption is reduced about 48% and the SNM is widened up to 56% compared to the conventional 6T SRAM at the expense of 2% leakage power and 3% write delay increase.