A Method of Design and Update for an Address Generator Using a Hybrid Method

[1]  Tsutomu Sasao,et al.  On the design of LPM address generators using multiple LUT cascades on FPGAs , 2007 .

[2]  C. G. Sodini,et al.  A ternary content addressable search engine , 1989 .

[3]  Teuvo Kohonen,et al.  Content-addressable memories , 1980 .

[4]  Nick McKeown,et al.  Routing lookups in hardware at memory access speeds , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[5]  Tsutomu Sasao.  A cascade realization of multiple-output function for reconfigurable hardware , 2001 .

[6]  Huan Liu.  Routing Table Compaction in Ternary CAM , 2002, IEEE Micro.

[7]  Munehiro Matsuura,et al.  An Implementation of an Address Generator Using Hash Memories , 2007 .

[8]  Tsutomu Sasao,et al.  A CAM Emulator Using Look-Up Table Cascades , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[9]  Kieran McLaughlin,et al.  Exploring CAM Design For Network Processing Using FPGA Technology , 2006, Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services (AICT-ICIW'06).

[10]  K. Pagiamtzis,et al.  A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme , 2004, IEEE Journal of Solid-State Circuits.

[11]  Steven A. Guccione,et al.  A Reconfigurable Content Addressable Memory , 2000, IPDPS Workshops.

[12]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[13]  Gordon J. Brebner,et al.  Mutable codesign for embedded protocol processing , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[14]  Tsutomu Sasao.  Design Methods for Multiple-Valued Input Address Generators , 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).