Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

[1]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[2]  Arnaud Virazel,et al.  Comparison of open and resistive-open defect test conditions in SRAM address decoders , 2003, 2003 Test Symposium.

[3]  Said Hamdioui,et al.  Importance of dynamic faults for new SRAM technologies , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[4]  Ad J. van de Goor,et al.  Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  Arnaud Virazel,et al.  Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[6]  Said Hamdioui,et al.  Detecting faults in the peripheral circuits and an evaluation of SRAM tests , 2004, 2004 International Conferce on Test.

[7]  Said Hamdioui,et al.  Detecting faults in the peripheral circuits and an evaluation of SRAM tests , 2004 .

[8]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[9]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[10]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[11]  Arnaud Virazel,et al.  Data retention fault in SRAM memories: analysis and detection procedures , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[12]  Arnaud Virazel,et al.  March iC-: an improved version of March C- for ADOFs detection , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..