Semiconductor memory device and arrangement method of memory cell array thereof

A semiconductor memory device and a method for arranging a memory cell array of the same are provided to reduce a layout area, to improve noise immunity by using a folded bit line structure, and to reduce the number of sense amplifiers in a sense amplifying unit. A semiconductor memory device includes a plurality of word line pairs(WL1 to WL8), a plurality of bit line pairs, and a memory cell array. The plurality of bit line pairs(BL1 to BL4B) are arranged vertically to the word lines. Each bit line pair are composed of a bit line and a reverse bit line adjacent to each other. The memory cell array are composed of first to fourth memory cells(MC1 to MC4). Each memory cell includes a transistor of a buried gate structure and a capacitor. The transistor is connected with the reverse bit line between first lines of one word line pair and the bit line between second lines of another word line pair.