A 10-bit 100-MS/s hybrid ADC based on flash-SAR architecture

This paper presents a 10-bit hybrid ADC which consists of the coarse flash ADC and the fine SAR ADC. A novel switching scheme is proposed and used in the hybrid architecture ADC. Compared with the MCS scheme, the proposed switching scheme reduces the capacitor requirement by almost twofold and improves the average switching energy efficiency by 81.22%. In order to achieve the required rail-to-rail input swing, the dynamic comparators with a rail-to-rail common-mode input range are adopted in the flash ADC. This hybrid ADC is designed in a SMIC 0.18µm CMOS technology and simulation result achieves an ENOB of 9.929-bit with an input signal near the Nyquist frequency. And the estimated power consumption is 2.49mW with a supply voltage of 1.8V.

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