A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs

This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.

[1]  Joel Nothman,et al.  SciPy 1.0-Fundamental Algorithms for Scientific Computing in Python , 2019, ArXiv.

[2]  Tom Hill,et al.  AXI 4 Interconnect Paves the Way to Plug-and-Play IP , 2009 .

[3]  M. Steyaert,et al.  A 1-V, 1-MS/s, 88-dB sigma-delta modulator in 0.13-/spl mu/m digital CMOS technology , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[4]  Kofi Makinwa,et al.  A Low Power Continuous-Time Zoom ADC for Audio Applications , 2019, 2019 Symposium on VLSI Circuits.

[5]  Francisco Serra-Graells,et al.  A Compact Switched-Capacitor Multi-Bit Quantizer for Low-Power High-Resolution Delta-Sigma ADCs , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  D.K. Su,et al.  A 0.7-V 100-dB 870-μW digital audio ΣΔ modulator , 2008, 2008 IEEE Symposium on VLSI Circuits.

[7]  David Lamb,et al.  A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[8]  Shanthi Pavan,et al.  A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth , 2019, 2019 Symposium on VLSI Circuits.

[9]  Ming-Dou Ker,et al.  Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process , 2008, IEICE Trans. Electron..

[10]  A. Hastings.  The Art of Analog Layout , 2000 .

[11]  Johan H. Huijsing,et al.  3.3 An 118dB DR CT IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers , 2006 .

[12]  Sujith Billa,et al.  15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[13]  Youngcheol Chae,et al.  A 1.2V 68µW 98.2DB-DR Audio Continuous-Time Delta-Sigma Modulator , 2018, 2018 IEEE Symposium on VLSI Circuits.

[14]  Derek Hummerston,et al.  An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz , 2017, 2017 Symposium on VLSI Circuits.

[15]  Francisco Serra-Graells,et al.  Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Hongxing Li,et al.  A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[17]  YuQing Yang,et al.  A 114 dB 68 mW chopper-stabilized stereo multi-bit audio A/D converter , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[18]  Terada,et al.  1.2-v, 16-bit Audio A/d Converter With Suppressed Latch Error Noise , 1997, Symposium 1997 on VLSI Circuits.

[19]  Francisco Serra-Graells,et al.  A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation † , 2017, Sensors.

[20]  Kofi A. A. Makinwa,et al.  15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[21]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[22]  Francisco Serra-Graells,et al.  An academic EDA suite for the full-custom design of mixed-mode integrated circuits , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[23]  Cong Liu,et al.  15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.