Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust- and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.

[1]  David Declercq,et al.  Density Evolution and Functional Threshold for the Noisy Min-Sum Decoder , 2014, IEEE Transactions on Communications.

[2]  P. Jonker,et al.  A defect-?and fault-tolerant architecture for nanocomputers , 2003 .

[3]  Ivan J. Fair,et al.  Density Evolution for Nonbinary LDPC Codes Under Gaussian Approximation , 2009, IEEE Transactions on Information Theory.

[4]  François Leduc-Primeau,et al.  Faulty Gallager-B decoding with optimal message repetition , 2012, 2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton).

[5]  Ahmed M. Eltawil,et al.  Fast error aware model for arithmetic and logic circuits , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[6]  Lorena Anghel,et al.  Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies , 2007, IWANN.

[7]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[8]  Michael G. Taylor Reliable information storage in memories designed from unreliable components , 1968 .

[9]  Shashi Kiran Chilappagari,et al.  Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates , 2006, 2006 IEEE International Symposium on Information Theory.

[10]  David Declercq,et al.  Finite Alphabet Iterative Decoders—Part I: Decoding Beyond Belief Propagation on the Binary Symmetric Channel , 2013, IEEE Transactions on Communications.

[11]  Lara Dolecek,et al.  Gallager B Decoder on Noisy Hardware , 2013, IEEE Transactions on Communications.

[12]  Rüdiger L. Urbanke,et al.  The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.

[13]  Alexios Balatsoukas-Stimming,et al.  Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage , 2014, IEEE Communications Letters.

[14]  H. Vincent Poor,et al.  Density evolution for asymmetric memoryless channels , 2005, IEEE Transactions on Information Theory.

[15]  David Declercq,et al.  Unconventional behavior of the noisy min-sum decoder over the binary symmetric channel , 2014, 2014 Information Theory and Applications Workshop (ITA).

[16]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[17]  David Burshtein,et al.  Design and analysis of nonbinary LDPC codes for arbitrary discrete-memoryless channels , 2005, IEEE Transactions on Information Theory.

[18]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[19]  Lav R. Varshney,et al.  Performance of LDPC Codes Under Faulty Iterative Decoding , 2008, IEEE Transactions on Information Theory.

[20]  Lara Dolecek,et al.  Gallager B LDPC Decoder with Transient and permanent errors , 2013, 2013 IEEE International Symposium on Information Theory.

[21]  Shashi Kiran Chilappagari,et al.  An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  David Declercq,et al.  Min-Sum-based decoders running on noisy hardware , 2013, 2013 IEEE Global Communications Conference (GLOBECOM).

[23]  Nicholas Pippenger,et al.  On networks of noisy gates , 1985, 26th Annual Symposium on Foundations of Computer Science (sfcs 1985).

[24]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[25]  Anna Gál,et al.  Lower bounds for the complexity of reliable Boolean circuits with noisy gates , 1991, [1991] Proceedings 32nd Annual Symposium of Foundations of Computer Science.

[26]  Daniel J. Costello,et al.  LDPC block and convolutional codes based on circulant matrices , 2004, IEEE Transactions on Information Theory.

[27]  Lara Dolecek,et al.  Analysis of finite-alphabet iterative decoders under processing errors , 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.