A High-Performance Closed-Loop Fourth-Order Sigma-Delta Micro-Machined Accelerometer

In this paper a high-performance closed-loop fourth-order sigma-delta (ΣΔ) micro-accelerometer is presented. After a introduction of sigma-delta accelerometer, system-level analysis and design of a fourth-order sigma-delta micro-accelerometer is given. The simulation result shows that an accelerometer with 107dB signal to noise ratio (SNR) and 17.5 bits effective number of bits (ENOB) is achieved. Through the root locus analysis, it is got that accelerometer is stable when quantization gain is bigger than 0.262. The accelerometer gets a good linearity and it becomes overload when input signal level is greater than -5dBFS.