Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.

[1]  Chor Ping Low,et al.  An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays , 2000, IEEE Trans. Computers.

[2]  Wu Jigang,et al.  Efficient reconfiguration algorithms for communication-aware three-dimensional processor arrays , 2013, Parallel Comput..

[3]  Hon Wai Leong,et al.  On the reconfiguration of degradable VLSI/WSI arrays , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Yi Wang,et al.  Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms , 2015, IEEE Transactions on Computers.

[5]  Jehoshua Bruck,et al.  Fault-Tolerant Meshes with Small Degree , 1997, SIAM J. Comput..

[6]  Wu Jigang,et al.  Reconfiguration algorithms for power efficient VLSI subarrays with four-port switches , 2006, IEEE Transactions on Computers.

[7]  Wu Jigang,et al.  Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches , 2007, IEEE Transactions on Computers.

[8]  Liang Chang,et al.  Optimal Reconfiguration of High-Performance VLSI Subarrays with Network Flow , 2016, IEEE Transactions on Parallel and Distributed Systems.

[9]  Jizhou Sun,et al.  Efficient Reconfiguration Algorithm for Three-dimensional VLSI Arrays , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

[10]  Masaru Fukushi,et al.  A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches , 2004, IEEE Transactions on Instrumentation and Measurement.