Lowphase noise andFast locking PLLFrequency Synthesizer fora915MHzISMBand

inthis paper, Lowphase noise andFastlocking PLL scheme inCMOS process integration. Thedetailed application Frequency Synthesizer ina0.18-um CMOSprocess ispresented. block diagram isshowninFig.1.(1) Thisthesis application isthe915MHzISM bandwirelessOneoftheunlicensed frequency islocated between 902MIHIz transponder upontheCPFSK(Continuous Phase Frequency Shiftand928MHz. Thisthesis application isonthe915MHzwireless Keying) modulation scheme. Frequency synthesizer designs basedcommunication. Thetransceiver employs aCPFSKmodulation uponself-biased techniques arepresented. ThePLL frequency schemeThetransceiver isalso embedded withRS-232C UART synthesizer designs achieve process technology independence, fixedsce.Duetoais1Suatio em e, RSK3UART damping factor fixed bandwidth tooperating frequency ratio, interface. Duetoitsmodulation scheme, CPFSK,inphase and broad frequency range, input phase offset cancellation, and,mostquadrature signal paths areexist atreceiver part. Andthis importantly. modulation schemeenables thepassband modulation using a A fully-integrated, 915MISMbandwireless transponder usingPLLfrequency synthesizer directly bychanging modulus ratio. CPFSKcommunication, frequency synthesizer inthefrequencyThissystemadopts a TDD (TimeDivision Duplexing) range of320M - 960MHzwithfrequency resolution of10MHZ, is architecture. Thusaccording tothebaseband status, this means designed in0.18pm CMOS process andsilicon performance is TXorRXmode,RFT/Rswitch canchange thesignal path. measured. Integer-N architecture ischosen forimplementation. It consumes 20mWofpower at1.8Vsupply andcore areais540,jm x II. FREQUENCYSYNTHESIZER ARCHITECTURE 450jLm. Themeasured phase-noises are-117.92dBc/Hz at10MHz offset, respectively, withlowsettling time less than3.3js. Thefrequency ofoscillators inRFtransceivers mustbedefined I. INTRODUCTION withveryhighaccuracy. Thefrequency mustbevaried insmall, Theexplosion ofthedigital communication market whichprecise steps. Thus, theerrorintheoutput frequency must consist ofwireless local-area networks, cordless telephone, remain below afewhundred hertz. cellular, andPCSapplications hasdriven thedemandforpotable Thearchitecture that usesanInteger-N divider canbesimply communication systems. These havethecommonrequirement showbyusing ablock diagram like Figure 2. vc_ r--t)iLPLS ~~~~MIODEM Phase-FRre.querlc v F(s) PA Q u >l£3 A QLa Mod. daXtI Loop-tldter A I IPLLIt ' .N1L L _ lFedlb&ckdivider