High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems
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[1] Jong-Wha Chong,et al. A memory efficient architecture of deblocking filter in H.264/AVC using hybrid processing order , 2009, 2009 International SoC Design Conference (ISOCC).
[2] Ilker Hamzaoglu,et al. An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).
[3] Tian-Sheuan Chang,et al. An in-place architecture for the deblocking filter in H.264/AVC , 2006, IEEE Trans. Circuits Syst. II Express Briefs.
[4] Youn-Long Lin,et al. An AMBA-compliant deblocking filter IP for H.264/AVC , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[5] M. Kthiri,et al. A parallel hardware architecture of deblocking filter in H264/AVC , 2010, 2010 9th International Symposium on Electronics and Telecommunications.
[6] Zhiyong Gao,et al. Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder , 2017, J. Signal Process. Syst..
[7] Yu-Lin Chou,et al. Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC , 2017, IEEE Transactions on Consumer Electronics.
[8] Liang-Gee Chen,et al. Architecture design for deblocking filter in H.264/JVT/AVC , 2003, 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698).
[9] Nouri Masmoudi,et al. A Novel Deblocking Filter Architecture for H.264/AVC , 2017, J. Signal Process. Syst..
[10] George Theodoridis,et al. An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC , 2014, 2014 6th International Symposium on Communications, Control and Signal Processing (ISCCSP).
[11] Oliver Chiu-sing Choy,et al. A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC , 2008, IEEE Transactions on Circuits and Systems for Video Technology.
[12] Sebastián López,et al. A scalable H.264/AVC deblocking filter architecture , 2013, Journal of Real-Time Image Processing.
[13] Gustavo Marrero Callicó,et al. An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering , 2008, IEEE Transactions on Consumer Electronics.
[14] Indrajit Chakrabarti,et al. High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter , 2015, IET Circuits Devices Syst..
[15] Jong-Wha Chong,et al. A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC , 2007, 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE'07).
[16] Ashraf A. Kassim,et al. A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC , 2006, IEEE Transactions on Consumer Electronics.
[17] Kuan-Hung Chen. 48 cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding , 2010, IET Circuits Devices Syst..
[18] Xiao Peng,et al. De-blocking Filter Design for HEVC and H.264/AVC , 2012, PCM.
[19] Stefan Winkler,et al. The Evolution of Video Quality Measurement: From PSNR to Hybrid Metrics , 2008, IEEE Transactions on Broadcasting.
[20] Jooheung Lee,et al. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration , 2010, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing.
[21] Chen-Yi Lee,et al. A memory-efficient deblocking filter for H.264/AVC video coding , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[22] Itu-T and Iso Iec Jtc. Advanced video coding for generic audiovisual services , 2010 .