SBNR processor for stack filters
暂无分享,去创建一个
[1] J. Astola,et al. Binary polynomial transforms and nonlinear digital filters , 1995 .
[2] Behrooz Parhami,et al. Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations , 1990, IEEE Trans. Computers.
[3] Keshab K. Parhi,et al. Parallel processing architectures for rank order and stack filters , 1994, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).
[4] Sos S. Agaian,et al. Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes , 1995, IEEE Trans. Signal Process..
[5] Jaakko Astola,et al. Adaptive Stack Filtering with Application to Image Processin , 1993, IEEE Trans. Signal Process..
[6] M. Andrews. A systolic SBNR adaptive signal processor , 1986 .
[7] James E. Robertson,et al. Logical design of a redundant binary adder , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).
[8] Tomás Lang,et al. Fast Multiplication Without Carry-Propagate Addition , 1990, IEEE Trans. Computers.
[9] Stanley L. Hurst,et al. Multiple-Valued Logic—its Status and its Future , 1984, IEEE Transactions on Computers.
[10] Edward J. Coyle,et al. Input Compression and Efficient Algorithms and Architectures for Stack Filters , 1993, IEEE Winter Workshop on Nonlinear Digital Signal Processing.
[11] Behrooz Parhami,et al. On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems , 1993, IEEE Trans. Computers.
[12] Behrooz Parhami,et al. Carry-Free Addition of Recorded Binary Signed-Digit Numbers , 1988, IEEE Trans. Computers.
[13] Hiroto Yasuura,et al. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.
[14] Bede Liu,et al. Design of cascade form FIR filters with discrete valued coefficients , 1988, IEEE Trans. Acoust. Speech Signal Process..
[15] Liangchien Lin,et al. Input compression and efficient VLSI architectures for rank order and stack filters , 1994, Signal Process..
[16] Keshab K. Parhi,et al. A fast VLSI adder architecture , 1992 .
[17] W. Edwin Clark,et al. On arithmetic weight for a general radix representation of integers (Corresp.) , 1973, IEEE Trans. Inf. Theory.
[18] Edward J. Coyle,et al. Stack filters , 1986, IEEE Trans. Acoust. Speech Signal Process..
[19] B. Liu,et al. A CMOS implementation of a variable step size digital adaptive filter , 1989, International Conference on Acoustics, Speech, and Signal Processing,.
[20] K. Chen. Bit-serial realizations of a class of nonlinear filters based on positive Boolean functions , 1989 .
[21] Sos S. Agaian,et al. Decompositional methods for stack filtering using Fibonacci p-codes , 1995, Signal Process..
[22] Dhananjay S. Phatak,et al. Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains , 1994, IEEE Trans. Computers.
[23] Tomás Lang,et al. On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.
[24] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[25] Kai-Yeung Siu,et al. An efficient implementation of stack filters , 1993, Proceedings of 27th Asilomar Conference on Signals, Systems and Computers.
[26] Dana S. Richards,et al. VLSI median filters , 1990, IEEE Trans. Acoust. Speech Signal Process..
[27] Bede Liu,et al. Decomposition of binary integers into signed power-of-two terms , 1991 .
[28] Edward J. Coyle,et al. Stack filters and the mean absolute error criterion , 1988, IEEE Trans. Acoust. Speech Signal Process..