Oxide Thickness Optimization for Digital Subthreshold Operation
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[1] Kaushik Roy,et al. Robust subthreshold logic for ultra-low power operation , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[2] Benton H. Calhoun,et al. Device sizing for minimum energy operation in subthreshold circuits , 2004 .
[3] Carlos Galup-Montoro,et al. Body-bias compensation technique for subthreshold CMOS static logic gates , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).
[4] Yu Cao,et al. Robust design of high fan-in/out subthreshold circuits , 2005, 2005 International Conference on Computer Design.
[5] A. Chandrakasan,et al. A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.
[6] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[7] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[8] B.C. Paul,et al. Device optimization for digital subthreshold logic operation , 2005, IEEE Transactions on Electron Devices.
[9] Kaushik Roy,et al. Robust ultra-low power sub-threshold DTMOS logic , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).
[10] Christofer Toumazou,et al. Nano-power subthreshold current-mode logic in sub-100 nm technologies , 2005 .
[11] Sachin S. Sapatnekar,et al. Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[12] S. Chakraborty,et al. Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications , 2007, IEEE Transactions on Electron Devices.
[13] Andrei Vladimirescu,et al. Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold , 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).
[14] K. Y. Lim,et al. A general approach to compact threshold voltage formulation based on 2D numerical simulation and experimental correlation for deep-submicron ULSI technology development [CMOS] , 2000 .
[15] B.C. Paul,et al. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices , 2005, IEEE Transactions on Electron Devices.
[16] Kaushik Roy,et al. Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] L.T. Clark,et al. An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage , 2006, IEEE Journal of Solid-State Circuits.