Design A New Stable And Low Power Bandgap Reference Circuit Based On Fin-FET Device
暂无分享,去创建一个
[1] Y. Yusoff,et al. Design and characterization of bandgap voltage reference , 2012, 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE).
[2] Dongpo Chen,et al. A 1.8V low noise threshold voltage reference generator with temperature and process calibration , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.
[3] Yueming Jiang,et al. A low voltage low 1/f noise CMOS bandgap reference , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[4] Anish Muttreja,et al. FinFET Circuit Design , 2011 .
[5] Paul Leroux,et al. A 4.5 MGy TID-Tolerant CMOS Bandgap Reference Circuit Using a Dynamic Base Leakage Compensation Technique , 2013, IEEE Transactions on Nuclear Science.
[6] Mohsen Imani,et al. Estimation of joint probability density function of delay and leakage power with variable skewness , 2013, 2013 International Conference on Electronics, Computer and Computation (ICECCO).
[7] Devrim Yilmaz Aksin,et al. Untrimmed 6.2 ppm/°C bulk-isolated curvature-corrected bandgap voltage reference , 2014, Integr..
[8] Mohsen Jafari,et al. Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing , 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
[9] G. Pei,et al. FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .
[10] Chenming Hu,et al. A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes , 2012, 2012 IEEE International SOI Conference (SOI).
[11] Dominique Schreurs,et al. A comprehensive review on microwave FinFET modeling for progressing beyond the state of art , 2013 .
[12] Abhirup Lahiri,et al. Design of sub-1-V CMOS bandgap reference circuit using only one BJT , 2012 .
[13] D. Hilbiber. A new semiconductor voltage standard , 1964 .
[14] Akira Matsuzawa,et al. Sub 1 V CMOS bandgap reference design techniques: a survey , 2010 .
[15] Gabriel A. Rincon-Mora,et al. Low-output-impedance 0.6 /spl mu/m CMOS sub-bandgap reference , 2007 .
[16] S. Dasgupta,et al. Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect , 2011, IEEE Circuits and Systems Magazine.
[17] G. Knoblinger,et al. Design and evaluation of basic analog circuits in an emerging MuGFET technology , 2005, 2005 IEEE International SOI Conference Proceedings.
[18] Mohsen Jafari,et al. Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET , 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
[19] D. Varadarajan,et al. A method for reducing the effects of random mismatches in CMOS bandgap references , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[20] Anne-Johan Annema,et al. A sub-1V bandgap voltage reference in 32nm FinFET technology , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.