Aging-Leakage Tradeoffs Using Multi-Vth Cell Library

Negative Bias Temperature Instability (NBTI) induced transistor aging has become one of the major reliability concerns in sub-micron circuit as technology scales. Transistor performance degrades over time and may eventually cause timing violations and circuit failure. Multi-Vth is known as a method to improve circuit performance with leakage and timing tradeoffs. In this paper, we propose a heuristic metric, which could be used to capture leakage and timing tradeoff during multi-Vth optimization. Our technique is an after-aging delay minimization problem under leakage power constraint. The experimental results on ISCAS85 benchmark circuits at 45nm node show up to 17% after-aging delay improvement within the predefined leakage power constraint.

[1]  Cecilia Metra,et al.  Low Cost NBTI Degradation Detection and Masking Approaches , 2013, IEEE Transactions on Computers.

[2]  Yu Wang,et al.  Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Bashir M. Al-Hashimi,et al.  BTI and leakage aware dynamic voltage scaling for reliable low power cache memories , 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

[4]  Hai Zhou,et al.  Leakage power optimization with dual-V/sub th/ library in high-level synthesis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[5]  Bashir M. Al-Hashimi,et al.  Aging Benefits in Nanometer CMOS Designs , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  P. Nicollian,et al.  Material dependence of hydrogen diffusion: implications for NBTI degradation , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[7]  Takayasu Sakurai,et al.  Analysis and future trend of short-circuit power , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  John M. Carulli,et al.  Impact of negative bias temperature instability on product parametric drift , 2004, 2004 International Conferce on Test.

[9]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[10]  Hao Luo,et al.  Aging and leakage tradeoff in VLSI circuits , 2015, 2015 10th International Design & Test Symposium (IDT).

[11]  Kenneth M. Butler,et al.  A design-for-reliability approach based on grading library cells for aging effects , 2013, 2013 IEEE International Test Conference (ITC).

[12]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[13]  Ing-Chao Lin,et al.  Leakage and Aging Optimization Using Transmission Gate-Based Technique , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[15]  D. Varghese,et al.  A comprehensive model for PMOS NBTI degradation: Recent progress , 2007, Microelectron. Reliab..

[16]  Yu Cao,et al.  Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[17]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[18]  S. Natarajan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[19]  Wei Zhang,et al.  NBTI-aware circuit node criticality computation , 2013, JETC.

[20]  Massoud Pedram,et al.  Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[22]  Min Chen,et al.  Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors , 2012, IEEE Design & Test of Computers.

[23]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[24]  Bashir M. Al-Hashimi,et al.  Reliable Power Gating With NBTI Aging Benefits , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.