Until recently FPGAs have been used almost exclusively to implement static circuits. Because FPGAs can be reprogrammed at any time, even in-system at run-time, interest in exploiting this mode of operation has steadily increased. One barrier to widespread use of Run-Time Reconfiguration (RTR) has been the lack of design tools. While tools such as JBits have begun to provide basic support for design entry, traditional verification tools such as simulators have been lacking. This paper discusses VirtexDS, a device level simulator for the Xilinx Virtex (tm) series. The approach taken by VirtexDS is to simulate at the device level, providing an interface which operates much like actual hardware. This approach not only supports simulation for run-time reconfiguration, but also interfaces easily to existing tools. In addition, this low-level simulation approach can provide higher performance than higher-level approaches to simulation.
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