Multi-Clustering Net Model for Placement Algorithms

Current placement algorithms aim at routable layouts with shortest wirelength and mostly minimize the total HalfPerimeter Wirelength (HPWL) of nets. A new clustering net model is proposed for better handling of high degree hyperedges, for which the HPWL can significantly underestimate wirelength. Splitting a net into several lower degree subnets, the total HPWL of the subnets estimates wirelength significantly better than HPWL of the original net. An efficient clustering approach is proposed with complexity linear on the number of pins. The final Steiner tree wirelength is improved with no or little penalty in runtime by transforming the circuit netlist between global and detailed placement stages accordingly to the new net model. The reduction in the wirelength also leads to shorter delays of circuits.

[1]  Teofilo F. Gonzalez,et al.  P-Complete Approximation Problems , 1976, J. ACM.

[2]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.

[3]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[4]  Joseph R. Shinnerl,et al.  Large-Scale Circuit Placement: Gap and Promise , 2003, ICCAD 2003.

[5]  Jason Cong,et al.  Routability-driven placement and white space allocation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[6]  Andrew B. Kahng,et al.  Implementation and extensibility of an analytic placer , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  M. Queyranne.  Performance ratio of polynomial heuristics for triangle inequality quadratic assignment problems , 1986 .

[8]  D.M. Mount,et al.  An Efficient k-Means Clustering Algorithm: Analysis and Implementation , 2002, IEEE Trans. Pattern Anal. Mach. Intell..

[9]  Peter Spindler,et al.  Fast and accurate routing demand estimation for efficient routability-driven placement , 2007 .

[10]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[11]  J. MacQueen.  Some methods for classification and analysis of multivariate observations , 1967 .

[12]  Chris C. N. Chu,et al.  FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Joseph R. Shinnerl,et al.  mPL6: enhanced multilevel mixed-size placement , 2006, ISPD '06.

[14]  Jarrod A. Roy,et al.  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Chih-Liang Eric Cheng.  RISA: accurate and efficient placement routability modeling , 1994, ICCAD.

[16]  Robert K. Brayton,et al.  Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[17]  David S. Johnson,et al.  The Rectilinear Steiner Problem is NP-Complete , 1977 .

[18]  Gi-Joon Nam,et al.  The ISPD2005 placement contest and benchmark suite , 2005, ISPD '05.

[19]  Chris Chu.  FLUTE: fast lookup table based wirelength estimation technique , 2004, ICCAD 2004.

[20]  Andrew B. Kahng,et al.  A tale of two nets: studies of wirelength progression in physical design , 2006, SLIP '06.

[21]  Andrew B. Kahng,et al.  Highly scalable algorithms for rectilinear and octilinear Steiner trees , 2003, ASP-DAC '03.