Evaluation of dynamically programmable cache machine with low power field programmable gate arrays (fpgas) and 3-dimensional multi-chip-module package

This dissertation introduces a new architecture for a reconfigurable computing processor. This processor is called Dynamically Programmable Cache (DPC). DPC is a novel multi-context FPGA architecture for embedded processors which offers flexibility, high memory bandwidth, and low execution times. DPC processors merge reconfigurable arrays with data cache blocks at various cache levels to create multi-level reconfigurable machines. The merging provides high memory bandwidth for FPGA cells, increases computation capacity per memory access, eliminates the bottleneck between the processor and chip, and reduces configuration latencies. The simple architecture, along with the large memory bandwidth, allows the FPGA to switch instantaneously to any of up to four FPGA configurations on a cycle-by-cycle basis. The flexibility of this machine lies in the fact that cache lines store data for the associated CPU, FPGA configurations, or both to create high levels of hardware utilization and area efficiency. The DPC machine is shown to offer 5X the speedup over an Altera FLEX10K for some applications.