An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50/spl deg/, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2/spl times/2 mm/sup 2/ chip consumes 1.1 W at 8 Gb/s with a 3-V supply.
[1]
M. Horowitz,et al.
Precise delay generation using coupled oscillators
,
1993,
1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2]
Teresa H. Meng,et al.
A 1-Gb/s, four-state, sliding block Viterbi decoder
,
1997,
IEEE J. Solid State Circuits.
[3]
R. Mactaggart,et al.
A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis
,
1997,
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[4]
William J. Dally,et al.
A tracking clock recovery receiver for 4-Gbps signaling
,
1998,
IEEE Micro.