25 W X-band GaN on Si MMIC

The first GaN on Si monolithic microwave integrated circuit (MMIC) has been demonstrated. The 2-stage X-band high power amplifier has a 2.5 mm input stage and an 11.4 mm output stage and its die size is 3 mm x 4.5 mm. At 10 GHz and 30 V drain bias, this MMIC achieved a pulsed output power of 25 W with 15 dB gain and 21% power-added efficiency. It produced 20 W of output power over the 8 to 10.5 GHz band when biased at 24 V. The GaN on Si MMIC was fabricated on TriQuint’s 4 inch GaAs manufacturing line and used an existing GaAs design. INTRODUCTION Gallium nitride (GaN) grown on silicon (Si) substrates is a very promising technology for microwave applications. It combines the low cost and ease of manufacturing associated with large diameter Si substrates and the demonstrated high power density and high efficiency offered by AlGaN/GaN devices. Although GaN on SiC substrates potentially offers higher frequency performance (e.g., • .D EDQG DQG EHWWHU thermal dissipation, SiC is prohibitively expensive and available mostly in 2 and 3 inch diameters that are incompatible with existing commercial GaAs fabs. There is also evidence that GaN on Si devices are more reliable than GaN on SiC [1], perhaps due to nonuniformity or poor quality of the SiC substrate relative to Si. Since 80-90% of the RF market is at X-band or below, the low cost and larger diameter of GaN on Si may lead to insertion in more applications. Most work on GaN on Si to date has targeted commercial applications such as cellular base station amplifiers near 2 GHz [2] with power output densities (Pout) up to 12 W/mm [3]. GaN on Si can also be used to build low cost, high power monolithic microwave integrated circuits (MMICs) at higher frequencies for military, communication or other applications. The first GaN on Si MMIC has been demonstrated by taking a MMIC that was designed for GaAs pHEMT and building it on a GaN on Si wafer. The 100 mm GaN on Si wafers were processed on the TriQuint Texas GaAs manufacturing fab. The resulting X-band GaN on Si MMIC had a similar frequency response to the GaAs MMIC but could be operated at much higher drain biases and delivered higher output power levels. With 24 V of drain bias, 20 W of output power was obtained over the 8 to 10.5 GHz frequency band compared to the nominal 8 W at 9 V that the part delivers on GaAs pHEMT material. This encouraging result indicates the great potential that GaN on Si has for both improving the performance and reducing the cost of MMICs. PROCESS The GaN on Si (111) wafers were grown by metalorganic chemical vapor deposition at Nitronex. Nitronex’s growth process allows high quality GaN epilayers to be grown on Si substrates by controlling thermal expansion and lattice mismatch-induced stresses [4]. The material described in this study consisted of a 600 nm AlN nucleation layer, a compositionally graded AlGaN transition layer, a ~800 nm unintentionally doped GaN buffer layer and a 300 Å AlGaN device layer with Al concentration of 20%. Typical sheet carrier concentrations of 6-7x10 12 cm and mobilities near 1300 cm/Vs were measured by Hall effect. Most GaN development at TriQuint has been done on 2 and 3 inch SiC substrates which are incompatible with the main 4 inch GaAs fab. Thus a separate research fab and equipment is needed to process GaN on SiC wafers. The 4 inch GaN on Si substrates allow production equipment and operators to be used which is inherently less costly and more efficient. There are still GaN specific processing steps that are needed, but they are done on standard equipment. Standard processing was done in the TriQuint GaAs fab except as noted below. GaN specific processing steps were used in the isolation, ohmic, gate and backside routes. Mesa etching was used for isolation. Inactive regions were defined and RIE etched in a chlorine based chemistry. With 80 V applied across a 10 μm isolated gap, less than 10 nA/mm of current was observed on all wafers. The ohmic metal was Ti/Al based and the RTA alloy was done at 850 oC. Ohmic deposition on wafers 1 and 3 and RTA alloy of wafer 1 was performed at Nitronex. A TriQuint RTA that aimed to copy the Nitronex process was used on wafers 2 and 3. Resulting contact and sheet resistances are given in Table 1 and averaged 0.6 ohm-mm and 720 ohms/square, respectively. This matches closely with wafers processed in the Nitronex fab on similar material. No gate recess etching was performed on these wafers. A dielectrically defined field plate gate was patterned and Pt/Au TABLE 1 OHMIC PROCESS SPLIT BETWEEN TRIQUINT (TQ) AND NITRONEX (NTRX) FABS GAVE SIMILAR CONTACT (Rc) AND SHEET (Rsh) RESISTANCE. was evaporated for the gate metal. The optical process defined a 0.30 μm gate length “T-shaped” gate. The rest of the frontside process used TriQuint’s standard flow for interconnect metal, capacitors and airbridges. The backside grinding to 4 mils and etching via holes through the Si substrate was done by Nitronex using standard Si process technology. An ICP etch of the GaN epitaxial layers was done at TriQuint to complete the via hole etch. This was followed by backside metallization and die separation by sawing. DC RESULTS AND YIELD Post gate metal DC results are summarized in Table 2. Wafer to wafer variations were small and standard deviations were near 4 %. Average I D,max of 570 mA/mm was measured at Vg = 2 V and Vd = 10 V and is about 10% lower than similar material processed at Nitronex. More careful GaN optimization of certain GaAs optimized processing steps such as asher and resist cleanup steps may improve I D,max. Twoterminal breakdown voltage (defined at 1 mA/mm) was near 90 V. Full wafer DC automated probing of the 451 MMICs per wafer showed good yields for 2 of the 3 wafers and standard deviations near 5 %. Several parameters were measured on both the input and output transistors of the MMIC which measure 2.5 mm and 11.4 mm, respectively. DC yields for wafers 1, 2 and 3 were 72, 5 and 85%, respectively. Wafer 2 was misprocessed during the liftoff of its first metal leaving most MMICs with unconnected gates and very low yield. Most of the yield loss on wafers 1 and 3 was due to pinchoff failures, possibly due to lifting gates or contamination under TABLE 2 POST GATE DC DATA OF THE 3 WAFERS. the gate. The pinchoff voltage of wafers 1 and 3 was –2.74 and –2.53 V, respectively, and standard deviations were 5.5% for both. Wafer maps show a slight increase in I D,max moving radially outward from the center, most likely attributable to a slight increase in Al % and growth temperature near the wafer edge, but the standard deviation was still only 5.4%. RF SMALL SIGNAL AND LOAD PULL RESULTS On wafer small signal measurements were collected on 4x75 μm devices from 1 to 40 GHz using an HP8510C network analyzer. H21 and MSG/MAG were calculated and values for the cutoff frequency, f t and maximum frequency of oscillation, fMAX, were extracted. Data were fit using an equivalent circuit model. Measured and modeled data for H21 and MSG/MAG are shown in Figure 1 from which an f t of 22 GHz and an f MAX of 74 GHz were extracted for wafer 1 at a drain bias of 20 V and 100 mA/mm. Figure 2 shows the decline of ft with increasing drain voltage but still above Xband even at 40 V. Figure 1. Measured and modeled H21 and MSG/MAG vs. frequency for wafer 1 showing ft of 22 GHz and fmax of 74 GHz when biased at 20 V and 100 mA/mm. Figure 2. Cutoff frequency, ft, vs drain bias at Id=100 mA/mm for 4x75 μm devices. Wafer Ohmic RTA Rc Rsh dep at at ohm-mm ohm/sq 1 NT RX NT RX 0.64 705 2 T Q T Q 0.65 726 3 NT RX T Q 0.51 717 AVG 0.60 716 Wafer Gm,max Idss Idmax Idleak Vp BVdg (mS/mm) (mA/mm) (mA/mm) (nA/mm) (V) (V) 1 189 379 572 1040 -2.65 99 2 173 343 555 380 -2.54 85 3 192 374 582 2730 -2.52 78 avg 185 365 57