Sense amplifier offset voltage analysis for both time-zero and time-dependent variability

Abstract This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

[1]  Mehdi Baradaran Tahoori,et al.  Aging mitigation in memory arrays using self-controlled bit-flipping technique , 2015, The 20th Asia and South Pacific Design Automation Conference.

[2]  T. Grasser,et al.  Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[3]  G. Groeseneken,et al.  Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.

[4]  A. Carlson.  Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability , 2007, IEEE Transactions on Device and Materials Reliability.

[5]  Francky Catthoor,et al.  Scaling of BTI reliability in presence of time-zero variability , 2014, 2014 IEEE International Reliability Physics Symposium.

[6]  A.B. Kahng,et al.  Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach , 2009, IEEE Transactions on Semiconductor Manufacturing.

[7]  Jörg E. Vollrath.  Signal margin analysis for DRAM sense amplifiers , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[8]  Said Hamdioui,et al.  Trends and challenges of SRAM reliability in the nano-scale era , 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[9]  Sachin S. Sapatnekar,et al.  Overcoming Variations in Nanometer-Scale Technologies , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[10]  Mario Konijnenburg,et al.  IoT: Source of test challenges , 2016, 2016 21th IEEE European Test Symposium (ETS).

[11]  Francky Catthoor,et al.  Bias Temperature Instability analysis of FinFET based SRAM cells , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Francky Catthoor,et al.  Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[13]  Jiajing Wang,et al.  Statistical modeling for the minimum standby supply voltage of a full SRAM array , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[14]  Ying Chen,et al.  Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[15]  B. Kaczer,et al.  Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.

[16]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[17]  Said Hamdioui,et al.  Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Francky Catthoor,et al.  Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates , 2014, IEEE Transactions on Device and Materials Reliability.

[19]  Shekhar Y. Borkar,et al.  Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.

[20]  N. Horiguchi,et al.  Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.

[21]  Francky Catthoor,et al.  Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[23]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[24]  W. Dehaene,et al.  A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[25]  Francky Catthoor,et al.  Degradation analysis of high performance 14nm FinFET SRAM , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Francky Catthoor,et al.  BTI impact on logical gates in nano-scale CMOS technology , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[27]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[28]  Mehdi Kamal,et al.  An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[29]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[30]  N. Collaert,et al.  Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[31]  Sandip Ray,et al.  The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction , 2016, IEEE Design & Test.

[32]  G. Groeseneken,et al.  Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.

[33]  Michael Nicolaidis,et al.  Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[34]  C. Cabral,et al.  A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[35]  Robert C. Aitken,et al.  Analytical model for TDDB-based performance degradation in combinational logic , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[36]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[37]  T. DeMassa,et al.  Threshold voltage variations with temperature in MOS transistors , 1971 .