Page buffer and multi-bit nonvolatile memory device including the same

According to one aspect of the invention, the memory cell array comprises a plurality of nonvolatile memory cell, the nonvolatile memory cells may be at least any one program from among the first, second, third and fourth threshold voltage state It said first, second, third and fourth threshold voltage states correspond to four different data values, defined by the first and second bits. A page buffer circuit is storing a logical value as the main data latch, depending on the voltage level of the bit lines responsive to a main latch signal to selectively flip the logic value of the main latch data. Sub-latch circuit sub- as latch circuits, depending on the voltage level of the bit line and the sub-sub for storing a logical value as the latch data responsive to the sub-latch signal to flip the logic value of the latch data optionally . Wherein the memory device is shipped to the threshold voltage state of the nonvolatile memory cell poison being operable in a read mode and a programming mode to program the threshold voltage state of the nonvolatile memory cell, the page buffer circuit, the bit to via the lines, inhibit the flipping of the logic value of the main latch data in the programming mode, the response to the sub-latch data. Multi-bit, a page buffer, a non-volatile semiconductor memory, the driving method