论文信息 - Simulation of a cmos rfc operation amplifier circuit with new results of dc gain

Simulation of a cmos rfc operation amplifier circuit with new results of dc gain

In this paper, we re-do simulation of a recycling folded cascode (RFC) op-amp which was published by Rida S. Assaad and et all, in IEEE Journal of Solid-State Circuits. The authors presented and simulated the RFC circuit to obtain DC gain using AC analysis only. They achieved to the results that with increasing the factor of k (the ratio of cross couple transistors in RFC circuit) the DC gain can be improved. But, we criticize their work scientifically and present a contrary result. We calculate and analyze the transconductance and output resistance of RFC op–amp using both DC and AC analysis. So we propose new results and prove this fact that with increasing k (1.5<k<3), the DC gain will be dropped from 51.8dB to 45.9dB. The simulation results are achieved using Hspise software in 0.18µm CMOS standard technology. Obtained results show a good coordination between DC and AC analysis to prove our claim.

Ghader Yosefi | Seyed Vahid Feizbakhsh

[1] Banafsheh Alizadeh,et al. An enhanced Folded Cascode op-amp in 0.18 µm CMOS process with 67dB dc-gain , 2011, 2011 Faible Tension Faible Consommation (FTFC).

[2] Abdollah Khoei,et al. Modified CMOS Op-Amp with Improved Gain and Bandwidth , 2006, IEICE Trans. Electron..

[3] Khayrollah Hadidi,et al. An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process , 2011 .

[4] José Silva-Martínez,et al. The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier , 2009, IEEE Journal of Solid-State Circuits.

[5] Ramón González Carvajal,et al. Class AB two stage and folded cascode OpAmps based on a squaring circuit , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).