Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.

[1]  P. R. Gray,et al.  Reference refreshing cyclic analog-to-digital and digital-to-analog converters , 1986 .

[2]  Paul R. Gray,et al.  A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .

[3]  John Tsimbinos,et al.  Error Tmle And Volterra Compensation Of A/d Converter Nonlinearities - A Comparison , 1996, Fourth International Symposium on Signal Processing and Its Applications.

[4]  Sameer Sonkusale,et al.  True background calibration technique for pipelined ADC , 2000 .

[5]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[6]  Yong Soo Cho,et al.  Adaptive precompensation of Wiener systems , 1998, IEEE Trans. Signal Process..

[7]  P.J. Hurst,et al.  A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[8]  Chung-Yu Wu,et al.  A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter , 1996 .

[9]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[10]  Paul R. Gray,et al.  A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter , 1988 .

[11]  Hae-Seung Lee A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC , 1994 .

[12]  R. Castello,et al.  A ratio-independent algorithmic analog-to-digital conversion technique , 1984, IEEE Journal of Solid-State Circuits.

[13]  R. de Figueiredo The Volterra and Wiener theories of nonlinear systems , 1982, Proceedings of the IEEE.

[14]  S. Haykin,et al.  Adaptive Filter Theory , 1986 .

[15]  Bruce A. Wooley,et al.  A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter , 1998 .

[16]  Y. Akazawa,et al.  Jitter analysis of high-speed sampling systems , 1990 .

[17]  Bang-Sup Song,et al.  A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[18]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.

[19]  Un-Ku Moon,et al.  Background digital calibration techniques for pipelined ADCs , 1997 .

[20]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[21]  Simon Haykin,et al.  Adaptive filter theory (2nd ed.) , 1991 .

[22]  Yun Chiu,et al.  Inherently linear capacitor error-averaging techniques for pipelined A/D conversion , 2000 .

[23]  Bang-Sup Song,et al.  A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter , 1995, IEEE J. Solid State Circuits.

[24]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[25]  Yoshinobu Kajikawa,et al.  The adaptive Volterra filter: its present and future , 2000 .

[26]  Bang-Sup Song,et al.  A 15 b 5 MSample/s low-spurious CMOS ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[27]  Hae-Seung Lee A 12 bit 600 kS/s digitally self-calibrated pipeline algorithmic ADC , 1993, Symposium 1993 on VLSI Circuits.

[28]  Paul R. Gray,et al.  A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS , 1996 .

[29]  S. H. Lewis,et al.  An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration , 2001 .