Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation
暂无分享,去创建一个
[1] Ernest Jamro,et al. Constant coefficient multiplication in FPGA structures , 2000, Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future.
[2] Behrooz Parhami,et al. Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations , 1990, IEEE Trans. Computers.
[3] Behrooz Parhami,et al. Carry-Free Addition of Recorded Binary Signed-Digit Numbers , 1988, IEEE Trans. Computers.
[4] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[5] Ahmed Bouridane,et al. Design and implementation of a high level programming environment for FPGA-based image processing , 2000 .
[6] Russell Tessier,et al. c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey ∗ , 1999 .