Wish Branches: Enabling Adaptive and Aggressive Predicated Execution

We propose a mechanism in which the compiler generates code that can be executed either as predicated code or nonpredicated code. The compiler-generated code is the same as predicated code, except the predicated conditional branches are not removed - they are left intact in the program code. These conditional branches are called wish branches. The goal of wish branches is to use predicated execution for hard-to-predict dynamic branches, and branch prediction for easy-to-predict dynamic branches, thereby obtaining the best of both worlds. Wish loops, one class of wish branches, use predication to reduce the misprediction penalty for hard-to-predict backward (loop) branches

[1]  J. Sartre,et al.  No Exit , 1944 .

[2]  Youngsoo Choi,et al.  The impact of If-conversion and branch prediction on program execution on the Intel/sup R/ Itanium/sup TM/ processor , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

[3]  Youngsoo Choi,et al.  The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor , 2001, MICRO.

[4]  Onur Mutlu,et al.  Wish branches: combining conditional branching and predication for adaptive predicated execution , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[5]  Brad Calder,et al.  Predicate prediction for efficient out-of-order execution , 2003, ICS '03.

[6]  Eric Rotenberg,et al.  Assigning confidence to conditional branch predictions , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[7]  Ken Kennedy,et al.  Conversion of control dependence to data dependence , 1983, POPL '83.

[8]  B. Ramakrishna Rau,et al.  The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs , 1989, Computer.

[9]  Onur Mutlu,et al.  2D-profiling: detecting input-dependent branches with a single input data set , 2006, International Symposium on Code Generation and Optimization (CGO'06).

[10]  John Paul Shen,et al.  Register renaming and scheduling for dynamic execution of predicated code , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[11]  Yale N. Patt,et al.  Facilitating superscalar processing via a combined static/dynamic register renaming scheme , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.