Study on power cycling test with different control strategies

Abstract Power cycling test is often used for the development of lifetime models of power semiconductor devices. The performance of power semiconductor devices in power cycling test is defined by the number of cycles to failure under certain given test conditions. In this work, power cycling tests with the same start test condition but different control strategies were performed. Except the standard control strategy, two other control strategies were realized by regulating three different adjustable parameters. It is also found that the definition of failure criteria in power cycling test will strongly influence the test results, which should also be defined appropriately.