Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC

This paper presents a low-complexity rate control (RC) framework for H.264/advanced video coding (AVC) encoders on embedded systems. We consider not only the rate-distortion performance but also its implementation complexity using an efficient hardware/software codesign. The proposed cost-effective macroblock level RC module works in hardware, and the frame-level RC is executed on the system CPU as software. It is less complex than the RC module adopted by H.264/AVC JM reference software, making it more suitable for embedded systems. Experiment results show that the proposed RC outperforms H.264/AVC JM, and the hardware implementation cost is low for an H.264/AVC video encoder.

[1]  Jyi-Chang Tsai Rate control for low-delay video using a dynamic rate table , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[2]  Jiro Katto,et al.  Mathematical analysis of MPEG compression capability and its application to rate control , 1995, Proceedings., International Conference on Image Processing.

[3]  Sanjit K. Mitra,et al.  Low-delay rate control for DCT video coding via ?-domain source modeling , 2001, IEEE Trans. Circuits Syst. Video Technol..

[4]  Chun-Jen Tsai,et al.  Out-of-loop rate control for video codec hardware/software co-design , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[5]  Seishi Takamura,et al.  MPEG-2 one-pass variable bit rate control algorithm and its LSI implementation , 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

[6]  Yang Song,et al.  A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P , 2007, 2007 IEEE Symposium on VLSI Circuits.

[7]  Tihao Chiang,et al.  Scalable rate control for MPEG-4 video , 2000, IEEE Trans. Circuits Syst. Video Technol..

[8]  Zhengguo Li,et al.  Adaptive Mad Prediction and Refined R-Q Model for H.264/AVC Rate Control , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[9]  Jiun-In Guo,et al.  A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Liang-Gee Chen,et al.  2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications , 2007, 2007 IEEE Symposium on VLSI Circuits.

[11]  Liang-Gee Chen,et al.  Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[12]  Hsueh-Ming Hang,et al.  The impact of rate control algorithms on video codec hardware design , 1997, Proceedings of International Conference on Image Processing.

[13]  Tihao Chiang,et al.  A new rate control scheme using quadratic rate distortion model , 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

[14]  Jiun-In Guo,et al.  A H.264 basic-unit level rate control algorithm facilitating hardware realization , 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

[15]  Xuan Jing,et al.  Improved Frame Level MAD Prediction and Bit Allocation Scheme for H.264/AVC Rate Control , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[16]  Yu-Wei Chang,et al.  Hardware oriented rate control algorithm and implementation for realtime video coding , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[17]  Gregory Doumenis,et al.  An Efficient H.264 VLSI Advanced Video Encoder , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.