Comparison and application of different VHDL-based fault injection techniques

Compares different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems. Some extensions and implementation designs of these techniques have been introduced. Also, a wide set of non-usual fault models have been implemented. As an application, a fault tolerant microcomputer system has been validated. Faults have been injected using an injection tool developed by the GSTF. We have injected both transient and permanent faults on the system model, using two different workloads. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Preliminary results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.

[1]  Daniel Antonio Gil Tomás Validación de sistemas tolerantes a fallos mediante inyección de fallos en modelos VHDL , 1999 .

[2]  Volkmar Sieh,et al.  VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[3]  Sumit Ghosh,et al.  On behavior fault modeling for digital designs , 1991, J. Electron. Test..

[4]  Barry W. Johnson,et al.  A Fault Injection Technique for VHDL Behavioral-Level Models , 1996, IEEE Des. Test Comput..

[5]  Régis Leveugle Fault injection in VHDL descriptions and emulation , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Pedro J. Gil,et al.  A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[7]  Alfredo Benso,et al.  Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[8]  Pedro J. Gil,et al.  A prototype of a VHDL-based fault injection tool , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  Pedro J. Gil,et al.  Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System , 1999, EDCC.

[10]  Javier Uceda,et al.  A fault model for VHDL descriptions at the register transfer level , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[11]  Jean Arlat Validation de la sûreté de fonctionnement par injection de fautes : méthode, mise en oeuvre, application , 1990 .

[12]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[13]  Eric Jenn Sur la validation des systèmes tolérant les fautes : injection de fautes dans des modèles de simulation VHDL , 1994 .