The personal communication systems of the future will augment the mobile phone concept to include multimedia services such as: digitised speech, data, e-mail, paging, facsimile, GPS, still images transmission, and real time video. To that end, we have employed delay insensitive asynchronous design techniques to implement a mathematical morphology processor for image coding using GaAs technology. For the implementation we introduce a modified version of the DCVSL family, in order to achieve ultra-fast data rates. Simulation of architecture implementation in GaAs MESFET 0.6 /spl mu/m technology demonstrates the reliability of this ASIC system for the high end image processing applications with a bit-rate of 4 Gbits/s. This is the first ever reported design of an asynchronous wave front morphological processor using GaAs technology for speed enhancement.
[1]
Abdelaziz Chihoub,et al.
Field-programmable gate array implementation of a systolic architecture for a morphology engine
,
1993,
Other Conferences.
[2]
Jos B. T. M. Roerdink,et al.
Mathematical Morphology in Image Processing
,
1993
.
[3]
Neil Weste,et al.
Principles of CMOS VLSI Design
,
1985
.
[4]
Anastasios N. Venetsanopoulos,et al.
Morphological methods in image coding
,
1992,
[Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[5]
Edward R. Dougherty,et al.
Mathematical Morphology in Image Processing
,
1992
.
[6]
Kamran Eshraghian,et al.
Principles of CMOS VLSI Design: A Systems Perspective
,
1985
.