Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation

“Curse of dimensionality” has become the major challenge for existing high-sigma yield analysis methods. In this paper, we develop a meta-model using Low-Rank Tensor Approximation (LRTA) to substitute expensive SPICE simulation. The polynomial degree of our LRTA model grows linearly with circuit dimension. This makes it especially promising for high-dimensional circuit problems. Our LRTA meta-model is solved efficiently with a robust greedy algorithm, and calibrated iteratively with an adaptive sampling method. Experiments on bit cell and SRAM column validate that proposed LRTA method outperforms other state-of-the-art approaches in terms of accuracy and efficiency.CCS CONCEPTS • Hardware → Failure prediction;

[1]  R. Tibshirani Regression Shrinkage and Selection via the Lasso , 1996 .

[2]  Bruno Sudret,et al.  Global sensitivity analysis using polynomial chaos expansions , 2008, Reliab. Eng. Syst. Saf..

[3]  Rob A. Rutenbar,et al.  Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[4]  Lara Dolecek,et al.  Breaking the simulation barrier: SRAM evaluation through norm minimization , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Xuan Zeng,et al.  High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  R. Tibshirani,et al.  Least angle regression , 2004, math/0406456.

[7]  C. C. McAndrew,et al.  Understanding MOSFET mismatch for analog design , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[8]  Wei Wu,et al.  REscope: High-dimensional statistical circuit simulation towards full failure region coverage , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  Lara Dolecek,et al.  Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Rob A. Rutenbar,et al.  Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Dongbin Xiu,et al.  The Wiener-Askey Polynomial Chaos for Stochastic Differential Equations , 2002, SIAM J. Sci. Comput..

[12]  Kelin Kuhn,et al.  Managing Process Variation in Intel’s 45nm CMOS Technology , 2008 .

[13]  P.R. Kinget Device mismatch and tradeoffs in the design of analog circuits , 2005, IEEE Journal of Solid-State Circuits.

[14]  Jun Yang,et al.  A Fast and Robust Failure Analysis of Memory Circuits Using Adaptive Importance Sampling Method , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[15]  Wei Wu,et al.  Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage , 2016, ISPD.